3d7701 monolithic gated delay line oscillator (series 3d7701) features ? all-silicon, low-power cmos technology ? ttl/cmos compatible inputs and outputs ? vapor phase, ir and wave solderable ? auto-insertable (dip pkg.) ? frequency range: 0.3mhz through 100mhz ? frequency tolerance: 0.5% typical ? temperature stability : 1.5% typical (-40c to 85c) ? vdd stability : 0.5% typical (4.75v to 5.25v) ? 14-pin dip available as drop-in replacements for hybrid delay line oscillator (dlo31f) functional description the 3d7701 delay line oscillator produc t family consists of fixed- frequency cmos integrated circuit osc illators. each package contains a single oscillator, which is gated and can therefore be synchronized to an external signal. the device frequenc y can range from 0.3mhz through 100mhz. the 3d7701 has two outputs that are in phase when the oscillator is running, and can be used as a drop-in replacement for the dlo31f hybrid oscillator. the 3d7701 is ttl- and cmos-compatible, capable of driving ten 74ls-type loads. it is offered in a standard 14-pin auto-insertabl e dip and a space saving surface mount 8-pin soic package. packages 14 13 12 11 10 9 8 1 2 3 4 5 6 7 o1 nc nc nc nc nc gn d vd d nc nc nc o2 nc en 3d77 01- x x dip - 14 3d77 01k - x x nc pins rem o ved 1 2 3 4 8 7 6 5 o1 nc nc gnd vd d nc o2 en 3d77 01 z-x x so ic -8 pin descriptions en oscillator enable o1 oscillator output 1 o2 oscillator output 2 vdd +5 volts gnd ground table 1: part number specifications output frequency (mhz) da sh number 25c vdd=5.00v -40c to 85c 4.75 3d7701 application notes operational description the 3d7701 delay line oscillator architecture is shown in figure 1. the internal delay line is composed of a number of delay cells connected in series and is compensated for thermal and supply voltage variations. a low-going edge on the en input starts the oscillator, with the o2 output responding immediately. the o1 output is delayed by ? cycle. the response of the output when the oscillator is disabled depends on the status of o2 when the en signal goes high, as shown in figure 2. if o2 is low, it will remain low, and the final pulse on o1 will be ? of the period. if o2 is high, it will go low as soon as en goes high, and the final pulse on both outputs will have a width smaller than ? the period. t e mp & vdd co m p ensati o n figure 1: 3d7701 functional diagram delay line en vdd gnd en o1 o2 o1 o2 f i g u r e 2: 3d7701 t i min g diag rams en o1 o2 5ns t y p 5ns t y p 5ns t y p doc #06023 data delay devices, inc. 2 12/5/2006 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
3d7701 application notes (cont?d) power supply and temperature considerations the delay of cmos integrated circuits is strongly dependent on power supply and temperature. the monolithic 3d7701 oscillator utilizes novel and innovative compensation circuitry to minimize the frequency variations induced by fluctuations in power s upply and/or temperature. the thermal coefficient is reduced to 250 ppm/c, which is equivalent to a variation, over the -40c to 85c operating range, of 1.5% from the room- temperature frequency setting. the power supply coefficient is reduced, over the 4.75v to 5.25v operating range, to 0.5% of the frequency setting at the nominal 5.0vdc power supply. these specifications hold for the lower frequencies only. for higher dash numbers, the variations will be slightly greater, as noted in table 1. it is essential that the pow er supply pin be adequately by passed and filtered. in addition, the pow er bus should be of as low an impedance construction as possible. pow e r planes are preferred. device specifications table 2: absolute maximum ratings p a r a m e t e r s y m b o l m i n m a x u n i t s n o t e s dc supply voltage v dd - 0 . 3 7 . 0 v input pin voltage v in - 0 . 3 v dd +0. 3 v input pin current i in - 1 . 0 1 . 0 m a 2 5 c storage temperature t st rg - 5 5 1 5 0 c lead temperature t lead 3 0 0 c 1 0 s e c table 3: dc electrical characteristics (-40c to 85c, 4.75v to 5.25v) p a r a m e t e r s y m b o l m i n t y p m a x u n i t s n o t e s static supply current* i dd 3 . 5 5 . 5 m a high level input voltage v ih 2 . 0 v low level input voltage v il 0 . 8 v high level input current i ih 1 . 0 a v ih = v dd low level input current i il 1 . 0 a v il = 0v high level output current i oh - 3 5 . 0 - 4 . 0 m a v dd = 4.75v v oh = 2.4v low level output current i ol 4 . 0 1 5 . 0 m a v dd = 4.75v v ol = 0.4v output rise & fall time t r & t f 2 . 0 2 . 5 n s c ld = 5 pf *i dd (dy namic) = 2 * c ld * v dd * f input capacitance = 10 pf ty pical w here: c ld = average capacitance load/output (pf) output load capacitance (c ld ) = 25 pf max f = device frequency (ghz) doc #06023 data delay devices, inc. 3 12/5/2006 3 mt. prospect ave. clifton, nj 07013
3d7701 silicon delay line automated testing test conditions input: output: ambient temperature: 25 o c 3 o c r load : 10k ? 10% supply voltage (vcc): 5.0v 0.1v c load : 5pf 10% input pulse: high = 3.0v 0.1v threshold: 1.5v (rising & falling) low = 0.0v 0.1v source impedance: 50 ? max. 10k ? 470 ? 5pf dev i c e under te s t di gi t a l s c ope rise/fall time: 3.0 ns max. (measured between 0.6v and 2.4v ) note: the above conditions are for test only and do not in any way restrict the operation of the device. o1 o2 out tr ig in re f tr ig figur e 3: t e s t s e tup de v i ce un de r t e s t (dut ) f r e q ue ncy / t i m e i n t e rv a l count e r pu l se ge ne ra t o r com p ut e r sys tem pr in ter en figur e 4 : t i ming dia g r a m 1/f os c en o2 2. 4v 1. 5v 0. 6v 2. 4v 1. 5v 0. 6v t rise t fall v ih v il 1. 5v 1. 5v 1. 5v t enb t dis doc #06023 data delay devices, inc. 4 12/5/2006 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
|
